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Author: Admin | 2025-04-28
The system, which will output these 2 data flows separately on two output ports together with "start of message" indication. Messages need to be output in the order of their appearance at the input (more strictly in the order of their first data (header) appearance).68. The king of the questions: tell about block you’ve designed.69. What are your 4 main characteristics?70. What will your manager tell about you?71. What will your manager tell you need to improve?72. Why do you leave? Why do you leave now? What will your colleagues say when they know you are leaving? 73. There is a wheel with sensor which produces a periodic clock-like wave of frequency proportional to the speed of wheel rotation. Design the circuit to determine whether the speed is “slow” or “fast”.74. Based on the previous question. There are two such wheels rotating with same speed but not in phase. Their two sensors produce two periodic waves. Design the circuit to determine what wheel is preceding and what is following.75. Design glitch-free (glitchless) clock mux. Already answered at https://www.eetimes.com/techniques-to-make-clock-switching-glitch-free/ and https://vlsiuniverse.blogspot.com/2017/03/clock-multiplexer.html.76. There is a processor and a memory to which it can access to read and write data. The data can be 8, 16 and 32b. ECC protection is applied to data. Design the system.77. There are N data flows in the system, while the flow is the stream of messages pertaining to this flow. The block aggregates messages per flow for M flows. M is much less than N. The following functions are supported:Add flow: when message pertaining to the flow which isn’t yet on block appears and there is enough storage space (number of already maintained flows on block is less than M), then add flow;Shift flow: when message pertaining to the flow which isn’t yet on block appears and there is no storage space (number of already maintained flows on block is equal M), then perform finalizing actions for LRU (least recently used) flow, drop it and add new flow;Use flow: when message pertaining to the flow which is already on block appears and the flow can be finalized (due to a certain number of messages aggregated until now), then perform finalizing actions for it and drop it;Each command is equipped with flow ID, designating the new flow in case of add and shift and the existing flow in case of use.Design only the mechanism for maintaining the order between flow, i.e. the mechanism to determine the LRU.78. The advanced variant of the previous question – don’t separate add and shift flow. The interviewee needs to come up with the idea of dropping the LRU flow when flows ordering mechanism is full.79. Propose bus encoding schemes to reduce
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